(j3.2006) BEQ, BNE?

[Keith Bierman]

http://www.nasdaq.com/symbol/altr ?

Using their fpga engines one could certainly build such a processor
As far as I recall their library elements and premade chips don't 

Multiple encoding a for fp 0 -0 were once common
E.g. CDC 6600++

How many systems have the issue for integers?

I certainly recall the older Standards allowing the -+0 issue.  Did we always allow it for integers or is that "new" ?



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On Jan 31, 2013, at 3:50 PM, Van Snyder <Van.Snyder at jpl.nasa.gov> wrote:

> On Thu, 2013-01-31 at 08:07 -0600, Bill Long wrote:
>> 
>> On 1/30/13 7:53 PM, Malcolm Cohen wrote:
>>>> I assume this is a theoretical question
>>> 
>>> Sorry, but I am with Van here.
>>> 
>>> It is so far from inconceivable that machines will have this kind of arithmetic
>>> that there are machines currently being produced with this kind of arithmetic.
>>> 
>>> We have gone to great lengths in the real, integer, and bit models in clause 13
>>> to avoid gratuitous machine dependencies, even to the extent of handling radices
>>> other than 2.
>> 
>> Parts of those lengths are in 13.3 where we make the interpretation of 
>> negative integers as bit sequences processor dependent, as well as 
>> pretty much everything related to bit sequences for non-binary integer 
>> representations.
> 
> Don't forget 4.4.2.2p1, which says that the integer zero value is
> considered to be neither negative nor positive, and that a signed zero
> has the same mathematical value as an unsigned zero.  The standard
> clearly contemplates platforms with two representations of zero.
> 
>> (Of course, I would have preferred to just have left BITS in the draft 
>> standard, avoiding the need for any of the B** functions.  But that 
>> position did not get consensus.)
> 
> You would have had my vote on BITS if you had specified a length
> parameter instead of a kind parameter.
> 
>> Ultimately, it is a question of where we put our efforts.  We can go to 
>> lengths to accommodate extinct (for good reason) hardware failures, or 
>> focus on challenges that we can be confident will be affecting 
>> scientific computing in the time scale of vendor implementations of the 
>> next standard.  Among those challenges, I don't see duplicate 
>> representation of integer values anywhere on the horizon.
> 
> Except, as Malcolm points out, they are being manufactured now.  I don't
> have as clear a crystal ball as Bill has, but I do have colleagues who
> keep close track of developments in chips with literally thousands of
> tiny processor cores.  There seem to be several new entrants into this
> game every year.  The last one they alerted me to is Altera (or is it
> Alterra?).  Who knows how many of those have (or will have) multiple
> representations of zero?
> 
> 
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